FPGA Implementation of Viterbi Algorithm for processing of Forward Error Control in Software Radio Receiver
نویسنده
چکیده
Convolution codes are one of the FEC codes that are used in every digital communication system. Convolution coding can be applied to block of data and also to a continuous input stream. Convolutional encoder can be viewed as a finite state machine.Viterbi algorithm is employed in wireless communications to decode the convolution codes. Such decoders are complex and dissipate large amount of power. Software Defined Radio (SDR) is realized using configurable hardware platforms. In this paper, a configurable viterbi decoder for SDR is described using a VHDL code. The proposed design of the viterbi decoder is considered so that it facilitates the decoder with different specifications. This paper proposes low power architecture viterbi decoder for developing and modeling a viterbi decoder for processing of forward error control in software radio receiver. The proposed design is simulated and synthesized by using Xilinx.The proposed design is implemented in Spartan 3e by using Xilinx
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